Integrated circuit design and test engineers seek to debug (or rootcause) all speed-related failures of an integrated circuit so that the integrated circuit can run faster. In order to debug or (rootcause) all speed related failures of a circuit, it is necessary to isolate timing related paths in the circuit so that these paths can alternatively be eliminated from the circuit, or can have their processing speed increased.
A technique of isolating the paths in an integrated circuit is to iteratively alter (by increasing for example) the frequency of suspected slow clocks in the clocking signal to the circuit of at least one particular clock(s) in an iteration, exercising the circuit with the clocking signal for each changed clocking signal in the iteration, and collecting the result of the exercising in each iteration by using latching elements coupled to the circuit to save the state of selected circuit portions at a determined time, and ascertaining in each iteration which if any circuit portions have failed to perform properly. In each iteration, a different particular pulse(s) in the clock signal is altered from a nominal value and/or the amount of the altering of at least one particular clock pulse is changed. A particular clock pulse can be altered by manipulating the clock frequency on a phase by phase basis through changing the rising edge timing or falling edge timing independently and/or in combination with each other.
The integrated circuit is disposed on at least one die. Coupled to the integrated circuit on the die(s) is a clock-generating circuit for typically, but not limited to, raising the frequency of a clocking signal generated by a coupled tester to a determined clocking signal frequency for the integrated circuit, and/or regulating the clocking signal. The integrated circuit includes a DFT (Designed For Test) pulse (or clock)-manipulating circuit coupled to the clock-generating circuit to manipulate at least one defined pulse in the clocking signal output generated by the clock-generating circuit. The pulse-manipulating circuit is used to iteratively alter a pulse (or clock) in the integrated circuit clocking signal as described above with reference to the technique of isolating a path.
A test system for the functional test of the integrated circuit conventionally includes a tester coupled to the integrated circuit through terminals, and the tester itself coupled to a computing device workstation. In operation, the tester in an iterative manner, transmits at least one test-data sequence of pulses, and a tester clock signal, to the on-die clock-generating circuit for execution of a functional test of the integrated circuit. The test-data sequence of pulses and the test clock input in each iteration, are generally first defined in the workstation, then transmitted from the workstation to the tester, then the tester generates the test data and test clock input, and then the tester transmits them to the die.
In each iteration, the tester also transmits to the die a binary coded message, or alternatively a trigger signal in combination with an offset defined in the binary coded message, to identify the pulse(s) to be manipulated in the output of the clock-generating circuit, and how each pulse to be manipulated is to be manipulated. The binary coded message is conventionally sent to the die as a header or preconditioning region of the test (or test pattern) in the tester. In an iteration, the workstation first defines the binary message content and trigger timing, the workstation transmits the trigger data and the binary message content to the tester, the tester constructs the binary message, and the tester transmits the trigger and the message to the die. In each iteration, each transmission of the trigger and the binary data message to the die causes the DFT to reinitialize, and to parse and to decode the message before clocking the manipulated clocking signal and executing the test data input. The workstation/tester—circuit-under-test interaction slows down significantly the throughput of testing.
What is needed is an apparatus and method to automatically select the pulse(s) to manipulate on the die(s) so as to eliminate the overhead of the tester and workstation generating a binary data message and the DFT re-initializing, in order to increase the rate of test.